1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method of forming a metal gate for a CMOS device using a replacement gate process wherein sidewall spacers are formed on a dummy electrode prior to forming the metal gate. In one embodiment a selective tungsten layer acts as an etch or CMP stop.
2) Description of the Prior Art
Polysilicon gate electrodes are commonly used in CMOS devices. However, as device densities continue to increase beyond the 0.2 .mu.m generation, polysilicon gates are adversely affected by poly depletion which can reduce performance by more than 15%. When a MOSFET is operated in an inversion mode, part of the gate applied voltage is dropped in the polysilicon due to the poor conductivity of the polysilicon. Because metal is a good conductor, metal gates do not suffer from poly depletion. While metal gates are an attractive alternative they are susceptible to metal migration during subsequent operations that are performed at elevated temperatures.
Another problem with high density (small dimension) devices is precise control of gate lengths. As devices continue to get smaller, precise control of gate lengths becomes critical to assure performance. One method for controlling gate lengths is by using a dummy or replacement gate process. In a replacement gate process, a dummy gate is formed of silicon dioxide or a polymer such as photoresist. An oxide layer is formed over the dummy gate. The dummy gate is removed leasing a gate opening, and the desired gate material is deposited into the gate opening. One problem with existing replacement gate processes is the limited ability to control the height of the dummy gate during removal of the overlying dielectric layer. Also, the etching process to form contact openings can cause oxidation of the source and drain regions leading to higher source and drain resistances.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,447,874 (Grivna et al.) shows a method for forming a dual metal gate using a damascene/CMP process. This method incorporates a large number of processing steps.
U.S. Pat. No. 4,745,082 (Kwok) shows a method for forming a metal gate by metal deposition and CMP back. In this method, additional processing steps are used and the spacers are removed.
U.S. Pat. No. 5,670,401 (Tseng) discloses a poly gate formed by a CMP process.
U.S. Pat. No. 4,963,501 (Ryan et al.) shows various metal gate processes.